1. Technical Field
Embodiments of the present invention generally relate to on-chip test logic and more particularly, but not exclusively, to structures for testing functionality of a protocol stack.
2. Background Art
Advances in semi-conductor processing and logic design have enabled an increase in the amount of logic that may be present on an integrated circuit (IC) device. As a result, successive generations of IC devices continue to shrink in size while supporting more storage, processing capability, communication bandwidth, etc. Some generally-available IC devices support interface standards—any of various Thunderbolt™ standards—which provide for data rates of 10 Gigabits per second (Gbps) and even up to or exceeding 20 Gbps.
As such high-speed IC devices continue to grow the number, variety and capability, manufacturers are starting to detect reliability problems. Such problems pose significant impediments to implementing next-generation improvements to device integration. Decreased link reliability also affects related technical areas, such as the need to securely provide firmware updates. The increasing integration, speed, and functionality of such IC devices poses challenges for manufacturers who need to debug, validate and launch products in a timely or cost-effective manner. Accordingly, there is expected to be an increasing premium placed on incremental improvements for providing solutions to test integrated circuitry.